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Systems/Low-level2026

Inventix VM

A 16-bit virtual machine with a custom instruction set, a JIT compiler to native x64, a paging MMU, and an integrated assembler and debugger.

Source
Systems/Low-level
IV

Overview

Inventix VM simulates a complete computer architecture, from a custom bytecode processor to a virtualized memory management unit with paging.

Highlights

  • Custom 16-bit CISC-like ISA with general-purpose registers, stack, and flags.
  • JIT compiler that translates Inventix bytecode into native x64 for near-native execution.
  • MMU with single-level paging: 16-bit virtual to 20-bit physical addressing with hardware-style R/W/X protection.
  • Integrated toolchain: a two-pass assembler, an interactive REPL shell, and a symbolic debugger with breakpoints, memory inspection, and single-stepping.
  • Memory-mapped video output and DOS-like software interrupts.

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A zero-dependency machine learning framework in roughly 2,800 lines of C11: arena allocator, reverse-mode autograd, multi-backend GEMM, and INT8 quantization.

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